1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device containing a reference capacitor circuit and applied to a microcomputer system having a memory mounted thereon, for example.
2. Description of the Related Art
FIG. 18 shows one example of a floor plan of the conventional nonvolatile semiconductor memory device, for example, a precharge type NOR flash EEPROM. A nonvolatile semiconductor memory device 11 includes memory cell arrays (MCA) 12, 13 each having a plurality of memory cells arranged in a matrix form. Row decoders (RDC) 14, 15 which select word lines (not shown), first regions 16, 17, second region 18, second control circuits (#2CONT) 19, 20 and signal wiring regions SGL1, SGL2 are arranged in the neighborhood of the memory cell arrays 12, 13. In the first regions 16, 17, sense amplifiers (S/A) which each detect and amplify data read out from a memory cell and the like are arranged. In the second region 18, a redundant column decoder (RDCDC) which selects a redundant bit line, a column decoder (CDC) which selects a bit line (not shown), a bias generating circuit (LVLGEN) which generates a bias voltage and a first control circuit (#1CONT) which generates various control signals are arranged.
Further, the nonvolatile semiconductor memory device 11 includes reference capacitor circuits 21, 22. When the potential of a bit line is detected by use of the sense amplifier, the reference capacitor circuits 21, 22 supply reference potential to the sense amplifier. The reference capacitor circuits 21, 22 are circuits each having the same capacitance as a parasitic capacitance of bit lines configuring the memory cell array. The parasitic capacitance of the bit lines depends on diffusion junction capacitance of the drain configuring the memory cell rather than wiring capacitance. Therefore, the conventional reference capacitor circuits 21, 22 respectively have the same number of dummy cells as the memory cells of the memory cell arrays 12, 13 and are formed with the same circuit configuration as that of the memory cell arrays 12, 13.
As a related technique, a memory in which a readout potential of a memory cell is compared with a readout potential of a dummy cell and sensed and amplified is developed (for example, refer to Jpn. Pat. Appln. KOKOKU Publication No. H7-15952). Further, memory cells in which data is written in order to deteriorate the dummy cells having the configuration equivalent to that of the memory cells at the same rate as the memory cells are developed (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2003-22680). In addition, a semiconductor memory device having reference cells whose gates are connected to discharging transistors is developed (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. H9-320283).
FIG. 19 shows the conventional reference capacitor circuit and FIG. 20 shows a part of the circuit. Further, FIG. 21 shows the layout of the reference capacitor circuit and FIG. 22 shows the equivalent circuit of a portion ranging from the reference capacitor circuit to the sense amplifier. As shown in FIG. 19, the sources (S) of dummy cells DMC0, . . . , DMC7 are connected to a source line SL and the drains (D) of the dummy cells DMC0, . . . , DMC7 are connected together by use of a metal wiring 23, for example. A reference potential is supplied to a connection node REF via the metal wiring 23. Further, the control gate of each dummy cell DMC is grounded via a dummy word line DWLN. Thus, since the conventional reference capacitor circuit has the same configuration as the memory cell array, the number of dummy cells of the reference capacitor circuit increases as the capacity of the memory cell array becomes larger and, as a result, the layout area is inevitably increased.
Further, since the conventional reference capacitor circuit has the same configuration as the memory cell array, it is necessary to provide the source wiring SL connected to the sources of the dummy cells and a VSS wiring 24 which supplies ground potential VSS to the source line in the reference capacitor circuit as shown in FIGS. 19 and 21. Therefore, if the VSS wiring 24 and metal wiring 23 are formed of a first-layered metal wiring, for example, restriction is imposed on the arrangement of the connection node REF which derives a reference potential from the metal wiring 23.
Further, in order to prevent occurrence of a leak, it is necessary to eliminate charges stored in the floating gate of the conventional dummy cell DMC by irradiation of ultraviolet rays, for example. Therefore, a large number of metal wirings cannot be arranged above the dummy cell. Further, in order to prevent an increase in the resistance of the VSS wiring 24, it is necessary to reduce the length of the VSS wiring 24 and arrange the reference capacitor circuit near the sense amplifier. Therefore, restriction is imposed on the arrangement of the reference capacitor circuit.
Further, if the gate oxide film of the dummy cell becomes faulty, the dummy cell is set in a normally leaking state. FIG. 22 shows the leak state of the dummy cell. In order to compare FIG. 22 with FIG. 14 which will be described later, in FIG. 22, common reference symbols are attached to the same portions as those of FIG. 14. As shown in FIG. 22, if a leak occurs, the precharge level of each portion is lowered in the precharge period. Further, in a next sense period, potential of the reference signal REF is rapidly discharged due to the leak of the dummy cell. Therefore, when an ON cell is detected, for example, two P-channel transistors configuring the sense amplifier are turned ON and the discharging operation for the bit line is delayed. In the worst case, the discharge potential of the bit line does not reach the ground potential and will be set at an intermediate level. In this case, in a next data readout period, an erroneous read operation occurs. That is, when data is read out from the ON cell, the data will be originally set at “1”, but the data is actually set at “0” (OFF cell). Further, even when data is correctly read out, an operation current in the precharge period will be increased due to occurrence of the leak. Therefore, it is desired to provide a nonvolatile semiconductor memory device in which the occupied area of the reference capacitor circuit can be reduced and occurrence of the leak current can be prevented.